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ACS02MS
Data Sheet November 1998 File Number 4540
Radiation Hardened Quad 2-Input NOR Gate
The Radiation Hardened ACS02MS is a Quad 2-Input NOR Gate. For each gate, a HIGH level on either A or B input results in a LOW level on the Y output. A LOW level on both the A and B inputs results in a HIGH level on the Y output. All inputs are buffered and the outputs are designed for balanced propagation delay and transition times. The ACS02MS is fabricated on a CMOS Silicon on Sapphire (SOS) process, which provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. These devices offer significant power reduction and faster performance when compared to ALSTTL types. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the ACS02MS are contained in SMD 5962-98601. A "hot-link" is provided on our homepage with instructions for downloading. www.intersil.com/data/sm/index.asp
Features
* QML Qualified Per MIL-PRF-38535 Requirements * 1.25 Micron Radiation Hardened SOS CMOS * Radiation Environment - Latch-Up Free Under Any Conditions - Total Dose. . . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si) - SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day - SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2) * Input Logic Levels. . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC) * Output Current . . . . . . . . . . . . . . . . . . . . . . . . 8mA (Min) * Quiescent Supply Current . . . . . . . . . . . . . . 100A (Max) * Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 12ns (Max)
Applications
* High Speed Control Circuits * Sensor Monitoring * Low Power Designs
Ordering Information
ORDERING NUMBER 5962F9860101VCC ACS02D/SAMPLE-03 5962F9860101VXC ACS02K/SAMPLE-03 5962F9860101V9A INTERNAL MARKETING NUMBER ACS02DMSR-03 ACS02D/SAMPLE-03 ACS02KMSR-03 ACS02K/SAMPLE-03 ACS02HMSR-03 TEMP. RANGE (oC) -55 to 125 25 -55 to 125 25 25 PACKAGE 14 Ld SBDIP 14 Ld SBDIP 14 Ld Flatpack 14 Ld Flatpack Die DESIGNATOR CDIP2-T14 CDIP2-T14 CDFP4-F14 CDFP4-F14 N/A
Pinouts
ACS02MS (SBDIP) TOP VIEW
1Y 1 A1 2 B1 3 Y2 4 A2 5 B2 6 GND 7 14 VCC 13 Y4 12 B4 11 A4 10 Y3 9 B3 8 A3
ACS02MS (FLATPACK) TOP VIEW
1Y A1 B1 Y2 A2 B2 GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC Y4 B4 A4 Y3 B3 A3
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
ACS02MS Die Characteristics
DIE DIMENSIONS: Size: 2390m x 2390m (94 mils x 94 mils) Thickness: 525m 25m (20.6 mils 1 mil) Bond Pad: 110m x 110m (4.3 x 4.3 mils) METALLIZATION: AI Metal 1 Thickness: 0.7m 0.1m Metal 2 Thickness: 1.0m 0.1m SUBSTRATE POTENTIAL Unbiased Insulator PASSIVATION: Type: Phosphorous Silicon Glass (PSG) Thickness: 1.30m 0.15m SPECIAL INSTRUCTIONS Bond VCC First ADDITIONAL INFORMATION: Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: 108
Metallization Mask Layout
ACS02MS
A1 (2) Y1 (1) VCC (14) Y4 (13)
B1 (3)
(12) B4
Y2 (4)
(11) A4
NC
NC
A2 (5)
(10) Y3
(6) B2
(7) GND
(8) A3
(9) B3
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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